-- Contador da Hora

library ieee;
use ieee.std_logic_1164.all;
use work.PCT_HORA.all;

entity HORA is
port(
		CLK, CLR: in std_logic;
		PRESETS1: in std_logic_vector(3 downto 0); -- 4
		PRESETS2: in std_logic_vector(3 downto 0); -- 2
		S_HORA: in std_logic;
		LOAD: in std_logic;
		INC: in std_logic;
		S1, S2: out std_logic_vector(6 downto 0)
	);
end HORA;

architecture DT_FLOW of HORA is
signal S_COUNT1 : std_logic_vector(3 downto 0);
signal S_COUNT2 : std_logic_vector(3 downto 0);
signal Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1 : std_logic;
signal S_INC : std_logic;
signal NEW_CLK : std_logic;
signal NEW_PRESETS1 : std_logic_vector(3 downto 0);
signal NEW_PRESETS2 : std_logic_vector(3 downto 0);

begin

	S_INC <= NOT(INC) AND S_HORA;
	NEW_CLK <= S_INC OR CLK;
	
	NEW_PRESETS1(3) <= PRESETS1(3) AND S_HORA AND NOT(LOAD);
	NEW_PRESETS1(2) <= PRESETS1(2) AND S_HORA AND NOT(LOAD);
	NEW_PRESETS1(1) <= PRESETS1(1) AND S_HORA AND NOT(LOAD);
	NEW_PRESETS1(0) <= PRESETS1(0) AND S_HORA AND NOT(LOAD);
	
	NEW_PRESETS2(3) <= PRESETS2(3) AND S_HORA AND NOT(LOAD);
	NEW_PRESETS2(2) <= PRESETS2(2) AND S_HORA AND NOT(LOAD);
	NEW_PRESETS2(1) <= PRESETS2(1) AND S_HORA AND NOT(LOAD);
	NEW_PRESETS2(0) <= PRESETS2(0) AND S_HORA AND NOT(LOAD);
	
	COUNT_4_BCD1 : COUNT_4_BCD port map (NEW_CLK, CLR, NEW_PRESETS1, Q4, Q3, Q2, Q1);
	COUNT_2_BCD2 : COUNT_2_BCD port map (Q4, CLR, NEW_PRESETS2, Q8, Q7, Q6, Q5);
	
	S_COUNT1(3) <= Q4;
	S_COUNT1(2) <= Q3;
	S_COUNT1(1) <= Q2;
	S_COUNT1(0) <= Q1;
	
	S_COUNT2(3) <= Q8;
	S_COUNT2(2) <= Q7;
	S_COUNT2(1) <= Q6;
	S_COUNT2(0) <= Q5;
	
	BCD_7SEG1 : BCD_7SEG port map (S_COUNT1,S1);
	BCD_7SEG2 : BCD_7SEG port map (S_COUNT2,S2);	

end DT_FLOW;